The present invention relates to a method of producing thin substrate layers, specifically thin semiconductor zones possibly containing integrated circuits.
It may be expedient for many present and future applications of electronic components and integrated circuits (ICs) in particular to restrict the overall thickness of these ICs or the semiconductor zones with the ICs to a few micrometers. Such thin circuits present a very low mass and have a very small overall height. They are mechanically flexible, adapt themselves to the thermo-mechanical behaviour of a substrate and reduce problems in disposal on account of their small volume. All these advantages may gain even more importance within the general framework of future disposable electronics. As early as to date thin electronic devices and circuits for fields of application such as flat panel displays, where ICs are bonded to glass, mechatronics, where the ICs are bonded to metal, and high-power electronics (transistors, thyristors, diodes with vertical conduction) are of great interest.
In silicon technology, integrated circuits are manufactured on substrates, the so-called wafers. These wafers consist of mono-crystalline silicon which present, in typical cases, a thickness of 700 xcexcm and a diameter of 200 mm at present and of 300 mm in the near future. The definition of the thickness of the substrates to 700 xcexcm offers several aspects in terms of manufacturing technology and also physics. For instance, the precision and the yield in slicing or sawing of the crystal rods drawn from the melt and their subsequent polishing, on the one hand, are important, on the other hand the mechanical stability and a sufficient thermal mass must be ensured during the actual processing of the ICs.
After the production of the integrated circuits or devices in terms of semiconductor technology the wafers and hence the individual chips of the wafer must be thinned to a residual thickness as small as 200 xcexcm and even down to 120 xcexcm at present in order to be suitable for integration into housings or on pc boards in particular.
Processing of the devices or circuits on cantilever wafers which are already thinned is normally ruled out because the mechanical stability, the thermal load-bearing capacity et. is by no means sufficient to this end below a thickness of 50 xcexcm. Moreover, the process development and the entire manufacturing equipment are designed and set for wafers of conventional thickness.
The thinning of the completely processed wafer Is normally realised by polishing. In this process the rear side of the wafer is mechanically removed by means of a polishing paste and suitable abrasive-carrying agents up to the desired residual thickness. Being a monocrystalline substance, silicon cannot be subjected to chipping operations. In the course of polishing rather so-called micro-fissures occur, which are due to the crystalline nature and which may propagate up to the device region of the wafer and destroy the functional operability of the circuits if the process is inappropriately managed. As a consequence of this situation the residual thickness of the silicon substrates, that can be achieved by polishing, is restricted, as a rule to a thickness corresponding to 5 to 10 times the size of the abrasive grains.
One possibility to solve this problem consists in the use of very fine abrasive grains up to diameters of a few hundreds of nanometers, This entails, however, a dramatic reduction of the removal rate so that the thinning process requires a very long time.
For a reduction of the residual thickness below the values occurring in the conventional grinding process it is necessary, as a rule, to employ particularly gentle polishing methods. An appropriate process which attempts to combine the advantages of grinding, wet-chemical etching and so-called CMP (chemical mechanical polishing) is published, for instance, in the paper by D. Bollmann et al., Abstract No. 2115, Proceedings, The Electrochemical Society Meeting, Paris 1997. As an alternative, wet and also dry etching methods have been tried. The latter processes, however, lead to a high thermal load on the substrate and the devices applied thereon, with the necessary amount of the removal rate.
On principle, these methods involve the thinning of the wafer after processing of the circuits. The processes leading to thinning are thus performed on a wafer on the surface of which the entire high added value in chip production is already accumulated. Faulty thinning correspondingly leads to a reduction of the yield and hence in high losses in value. Moreover, the observation of the desired residual thickness is rendered rather difficult on account of the reduced possibility of (local) measurement of the residual thickness, which is impaired by the implemented devices.
A fundamental way out of the problems Involved in thinning of wafers presenting a high accumulated added value and in the complex thickness measurement consists in the application of so-called SOI wafers. SOI wafers carry an insulating layer buried just below the surface, as a rule in the form of an SiO2 layer. There are several methods available for the production of such SOI wafers (cf., for instance, W. P. Maszara et al.: xe2x80x9cSOI Materials for Mainstream CMOS Technologyxe2x80x9d, in: SOI Technology and Devices VII, ed.: S. Christoloveanu, The Electrochemical Society Proceedings 97-23, 1997) which will be outlined in the following.
In SOS (silicon on sapphire) techniques an epitactical silicon layer is deposited on a polished Al2O3 crystal. This approach is successful as a result of the approximately equal lattice constant of both materials. However, crystalline Al2O3 wafers must be used, which renders this method very expensive and is applicable only in the case of extremely high-price applications.
In ZMR (zone melting recrystallization) technique poly-silicon is deposited on a wafer covered with SiO2 and then crystallised by a local fusing and solidifying process. The crystal quality, the crystallite size, etc. of these wafers does, as a matter of fact, no longer satisfy the demands current in today""s CMOS technology.
In the SIMOX (Separation of implanted oxygen) technique a high-dose ion implantation just below the surface of the silicon wafer creates a stoichiometric SiO2 layer which, in the case of an appropriate process management, i.e. thorough healing of the crystal damage caused by implantation, leaves the extremely thin silicon layer monocrystalline that is located thereabove and will carry devices later on.
In the BESOI (bonded etched-back silicon on insulator) technique two oxidized silicon wafers are fixedly fastened on each other by thermal bonding and covalent bonds so established. Then one of the two wafers is thinned back to the useful thickness. A specific variant of the BESOI technology (xe2x80x9cSmartCut(copyright) OR IonCut) uses special methods of thinning which are based on the implementation of a layer created by means of ion implantation and buried below the surface, along which layer the useful layer is split off that is bonded onto the second wafer (manipulating) wafer. This may be achieved by forming gas bubbles by means of hydrogen or helium implantation (cf. European Patent EP-A 0 533 551 or M. Bruel et al. in_xe2x80x9cUnibond SOI Wafers Achieved by Smart-Cut(copyright) Processxe2x80x9d in: SoI Technology and Devices VIII, ed.: S. Christoloveanu, The Electromechanical Society Proceedings 97-23, 1997) or by detaching a fusing intermediate layer (cf. German Patent DE 1{circumflex over ( )}95 46 179 A1). In both cases the production of a BESOI wafer is successful without repeated grinding or etching of major parts of a monocrystalline wafer laboriously produced before.
SOI wafers produced according to the SIMOX and BESOI processes have been developed up to a stage ready for application in the past few years. They are applied in the fields of application high-temperature electronics and xe2x80x9clow power electronicsxe2x80x9d to an ever-increasing extent and are commercially available in high numbers of units.
Such SOI wafers may be used for the production of extremely thin ICs. The subsequent removal of the thick carrier wafer by grinding, wet or dry chemical etching, etc. may then be stopped expediently at the buried layer. In the case of mechanical grinding, and specifically its refined form of chemical mechanical polishing (CMP) the buried SiO2 layer may serve as the mechanically hard stop layer. Furthermore, it is possible that mechanical defects such as micro-cracks cannot or only hardly penetrate through the amorphous SiO2 layer. In the case of wet chemical down-etching the high selectivity (better than 1:100) of the normally oxidizing silicon etching process results in a reliable etching stop at the buried oxide layer. In the case of the less selective dry etching processes, e.g. by application of NF3 plasma, the SiO2 layer may equally serve as selective stop layer. In view of the decreasing lateral conductivity, furthermore a local self-restriction of the etching process may be utilised.
One advantage in the application of SOI wafers resides in the aspect that the process resulting in subsequent thinning, i.e. the implementation of a buried layer underneath the silicon of the useful wafer, is performed before the processing proper in terms of semiconductor technology. As a consequence, firstly a high added value is not endangered, and secondly it is possible to use particularly simple optical or even acoustic measures of measuring the thickness because at this stage the wafer does not yet present any local structures, metals, etc. which render a non-contacting and precise measurement of the thickness more difficult or preclude it entirely.
However, the removal of the thick manipulating wafer by means of grinding or etching means that the monocrystalline silicon is destroyed over a substantial thickness, with a resulting expenditure in terms of time.
The present invention is therefore based on the problem of proposing a low-cost and rapid method of producing thin substrate layers, which is suitable to produce extremely thin ICs and avoids the afore-described problems.
This problem is solved with the method according to claim 1. Expedient embodiments of the method are the subject matters of the dependent claims. Moreover, the claims 29 to 47 define substrate systems which constitute an essential key product in realising the method.
In the inventive method, which will also be referred to as RevSOI (reversible SOI technique) a first substrate and a second substrate are bonded to each other by their faces via one or several intermediate bonding layers. At least one of the bonding layers or the face of one of the substrates is so configured that it presents channelshaped recesses permitting a lateral penetration of an etching agent. Subsequently, the first substrate is thinned from the rear side down to a thin substrate layer. This thin substrate layer is subsequently detached from the second substrate by the introduction of the etching agent into the channel-shaped recesses.
The two substrates are preferably semiconductor wafers for the production of ICs.
These wafers are processed in the same manner as that common within the general framework of IC or single-device production. Sagging does not occur on the wafers as long as the width of the channels (preferably 0.1-2 xcexcm) ranges at a fraction of the thickness of the useful layer of the semiconductor layer (typically 0.5-20 xcexcm).
After processing the structured bonding layer serves as sacrificial layer. This layer is laterally accessible, at any time, either from the side of the wafer or, in the case of a preferred embodiment, as soon as the hermetically sealed wafer edge is removed/opened. This is automatically done particularly when the wafer is subdivided to form chips. Before, the thin chips are expediently fixed on a carrier substrate.
The separation of the useful layer from the bulk layer is preferably carried out by wet chemical etching. In this step the etching agent (such as HF) is aspirated into the channels under the effect of capillary forces. The driving forces are the chemical reaction and the surface tension. The rate of flow or the throughput quantity, respectively, is described in approximation by the Hagen-Poiseuille law and depends on the channel lumen in the fourth power. In large-area chips or generally in the separation of large-area wafer zones the removal of the reaction products (e.g. SiF4) may be assisted by ultrasound, centrifugal force, thermal gradients (generated, for instance, by means of IR laser radiation) etc.
Moreover, vertical holes or slots may be provided or etched in the useful layer for the supply and extraction of the etching agent. For supplying or extracting the etching agent, the cleaving or sawing frame produced between the chips is expediently used.
The channel-shaped recesses need not necessarily extend along linear orientations. They need not present a rectangular cross-section either necessarily. In particular, the vertical walls or edges of the channels may also present an orientation varying from 90xc2x0 relative to the surface. Due to the specific engineering features of the etching operation, particularly in the case of etching under the mask in wet chemical etching, this edge bevelling may occur all by itself. On the other hand, however, special methods may be applied for edge bevelling or edge projection. Edge projection or cantilevering leads to the advantage of a relative enlargement of the bonding oxide area. Methods of taking an influence on the inclination of the etching edge are common to those skilled in the art within the general framework of the wet and dry etching techniques applied in semiconductor technology.
The aforementioned method may be extended or modified by the provision that the channels are not or not exclusively created in the bonding layer or layers but rather completely or partly in the substrates as such. In the case of a rectangular cross-section, this may lead to an enlargement of the lumen. A practical limit is set by the mechanical characteristics of the substrates (buckling under thermal strain, warping).
In particular, one can dispense with an oxide cover in at least one of the two wafers to be bonded. In this case the natural oxide, which is always present on wafers exposed to air, serves as bonding area.
In a preferred embodiment the fact is utilised that the buried insulating layer is freely accessible in BESOI wafers before both wafers are joined to form the BESOI assembly. It is also accessible for structuring of the bonding oxide in particular. One or both of the two wafers typically carries an SiO2 layer roughly 1 xcexcm thick. Prior to joining trenches are etched in one or both oxides, to which end the wafer edge carries a coherent annular oxide zone. Then both wafers are joined by thermal bonding in the usual manner, and one of the two wafers is thinned by means of one of the current thinning methods (grinding, etching, lonCut) described with respect to the BESOI technique to achieve the desired thickness of the useful layer.
Subsequently, circuits are formed with the usual technology on this BESOI wafer. During production, for which thermal and also vacuum or gas phase processes in particular are employed, the wafer is hermetically closed on the edge by the oxide ring. After completion of the circuits and opening of the coherent edge layer located on the wafer or also after subdivision of the wafer into chips the buried oxide layer, specifically the channels in the oxide provided therein, is laterally accessible. An etching agent such as hydrofluoric acid may penetrate into these channels and etch into the bonding oxide. The thin chip, which is preferably previously fixed by its face on a holding substrate for mechanical support, is typically detached within the range of minutes in the case of edge lengths of roughly 10 mm.
The detachment is a low-price wet chemical process which hardly exposes the chip and the added value integrated thereon to any risk.
It is particularly simple to check the thickness of the layer in thinning of the BESOI wafer by the presence of the burled cavities (trenches) with local resolution by means of acoustical microscopy.
As an alternative, the lonCut technique is applicable where grinding and measurement of the thickness of the layer are avoided.
The trenches present in the bonding layer produce an expedient effect on the bonding operation. It is common knowledge that wafers with a scratched surface have better bonding properties. This is traced back to the easier diffusion of residual gases, adsorbed moisture, etc. during the beginning bonding operation for which the presence of water (hydrophilic surface) is expedient.
The wafer edge or possibly also various elementary zones are preferably free of laterally accessible channels. This can be clearly seen both in FIG. 2b and in FIG. 3. The wafer should be hermetically sealed after bonding and tolerate all processes applied within the general framework of semiconductor device production.
The BESOI bonding process may be performed in particular in a vacuum or equally in special oxidizing or reducing atmospheres.
One advantage of accessibility of the sacrificial layer or xe2x80x9czipper layerxe2x80x9dduring the production of the RevSoi wafer resides in the fact that the cavities may be filled with specific gases.
In an expedient embodiment the bonding operation is performed with the addition of trace gases, helium in particular. On account of the enclosed gas it is particularly simple to check the bonded wafer for tightness (helium leakage test).
In another embodiment doping gases are enclosed in order to create a highly doped buried layer or a gettering layer.
The essential feature of the lateral accessibility of the insulating oxide layer may also be utilised in an approach to metallize the internal surfaces of the channels by means of a liquid or a gaseous metal compound and organometallic compounds in particular.